The amplifier according to the invention is particularly well adapted to amplify output signals of circuits produced by CMOS technology.
Reading amplifiers must keep two bit lines at predetermined, stable voltage levels representing a corresponding binary value. Typically, one of these levels corresponds to the ground voltage of the circuit, while the other level is that of a source of supply voltage. In such arrangements, reading amplifiers must meet a constraint having to do with the speed of operation, on the one hand, and on the other they must be designed to consume as little power as possible.
U.S. Pat. No. 4,551,641 describes a CMOS amplifier device comprising a first amplifier made with the aid of cross-connected NMOS transistors, which under the influence of a control signal effects the connection to ground of the bit line having the voltage that is closest to the ground voltage. Under the influence of a second control signal, a second amplifier using cross-connected PMOS transistors has the effect of putting the second bit line in communication with the supply source. The control signals of the two amplifiers are clock signals, phase shifted with respect to one another.
While the aforementioned circuit does attain amplification of the bit lines, it necessitates the presence of two clock signals, with a phase shift that must be sufficient to activate the second amplifier once the first bit line has been discharged sufficiently. If the amplifier having PMOS transistors is triggered too soon, before the first bit line has been discharged sufficiently, the two amplifiers would create a short-circuit path between the supply source and ground. This is a major disadvantage, especially in the case where a plurality of amplification devices are used to amplify the output of a register or operator including a large number of bit lines, each pair of bit lines being connected to such an amplification device controlled by the signals originating in a single clock.
In an application as just described, all the amplifiers with PMOS transistors are activated simultaneously, and accordingly a sufficiently great delay must be provided between this activation and that of the amplifiers with NMOS transistors, to prevent the aforementioned short circuit of any pair of bit lines. Moreover, this delay must also take into account the dispersion in the properties of the circuits that is inherent in their manufacture. The phase displacement between the activations of the two amplifiers must be exaggerated, which necessarily makes the amplification function slower. Otherwise, there is an increased risk of creating short-circuit paths between the supply and the ground, hence increasing power consumption.